Top Tech Jobs & Startup Jobs in Boston, MA

Lead technology strategy and system architecture for next-generation wireless infrastructure. Apply AI/ML to RAN (L1/L2+) and transform core to agentic AI-based packet core. Prototype GPU-accelerated algorithms, engage partners and standards bodies, and drive performance optimizations and new edge applications (ISAC, SemCom, Physical AI).

Design and implement an LLVM-based JIT backend for NVIDIA GPUs, develop compiler passes and optimizations to meet performance and compile-time targets, collaborate with hardware and application teams to resolve issues, apply modern compiler technologies, and influence future GPU architectures.

The role involves developing backend infrastructure features, ensuring high performance, debugging, collaborating cross-functionally, and optimizing code for cloud-based simulations.

As a Senior Solutions Architect, you will lead GPU-accelerated AI solutions development in healthcare, working alongside pharma companies to optimize simulations and robotic systems. You'll implement projects from concept to deployment while collaborating with various stakeholders.

As a Principal Software Engineer, you'll develop software systems for NVIDIA's rack-scale infrastructure, defining software architecture, collaborating across teams, mentoring engineers, and ensuring high-quality technical decisions in complex environments.

Analyze and run HPC applications to improve performance, assist in GPU acceleration, advise engineering teams on optimization opportunities.

Lead partner and customer engagements to design, build, and operationalize large-scale HPC and AI hybrid computing solutions. Provide hands-on cluster architecture, deployment, debugging, demos, and POCs using NVIDIA compute, networking, and software stacks. Collaborate with engineering and executives to solve complex low-latency, cloud-native AI factory problems.

Design and build developer tools to improve deep neural network design and performance. Translate requirements into designs, own development, and collaborate with architects and management. Stay current with deep learning research and become a domain expert to enable high-performance model design and optimization.

Lead hardware-software co-design for LLM inference: drive and document architecture, build executable C++ hardware models, optimize performance with good algorithms and parallelism, diagnose cross-team chip and subsystem issues, and automate workflows to improve efficiency.

Lead full-flow physical implementation for LPU ASICs: synthesis, floorplanning, place & route, timing closure, UPF/LEC low-power flows, and tapeout. Collaborate with IP, front-end, PnR and sign-off teams to optimize PPA and resolve bottlenecks. Architect automated, data-driven EDA methodologies, implement scripts and AI-assisted optimizations, and ensure sign-off quality including power grid, EMIR, and DFT integration for high-speed SerDes blocks.