Top Tech Jobs & Startup Jobs in Boston, MA

Design and verification engineer responsible for verifying high-throughput Ethernet silicon products using constrained-random methodologies, SystemVerilog, and UVM. The role includes developing testbench structures, assertions, coverage closure, and verification across the full design lifecycle. Responsibilities involve collaboration with global architecture and design teams, supporting rapidly evolving AI/ML accelerator devices, and providing opportunities for technical leadership.

Leads strategic customer engagements for ValueOps enterprise portfolio planning and agile management solutions. Responsibilities include aligning solutions to customer value, documenting business requirements, conducting product demonstrations and proofs of value, developing adoption roadmaps, managing account engagement information, coordinating internal teams, and supporting customer adoption and marketing activities.

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

Provides senior-level technical consulting for mainframe infrastructure environments and Broadcom Software products. Responsibilities include solution architecture, product implementation and upgrades, integrations, demonstrations, proofs of concept, troubleshooting, technical documentation, customer presentations, and post-implementation support. The consultant advises clients and management on infrastructure strategies and works with account teams to design solutions. Requires expertise in z/OS, Broadcom mainframe tools, REXX or HLASM, and major mainframe subsystems and security managers. Client-site travel is required.

Design and implement virtual CPU and memory features for Broadcom's VCF products. Work on low-level OS/kernel internals, x86_64 CPU virtualization, and related assembly/C code to enable CPU ISA updates, memory virtualization, and monitor architecture improvements.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.