Broadcom Jobs

ASIC Design Verification Engineer

Broadcom

ASIC Design Verification Engineer

Posted Yesterday

Be an Early Applicant

In-Office

Irvine, CA

129K-207K Annually

Expert/Leader

In-Office

Irvine, CA

129K-207K Annually

Expert/Leader

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.

The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers.

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other. Constrained random verification methodologies with experience driving completion via coverage closure.

Preferable to have skills with SV and UVM, well versed in OOP

Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $129,400.00 - $207,000.00.
 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Similar Jobs

Waymo

ASIC Design Verification Engineer

8 Days Ago

In-Office

175K-215K Annually

Mid level

175K-215K Annually

Mid level

Automotive

Design and execute comprehensive verification plans for custom silicon, developing UVM/SystemVerilog testbenches, reference models, and stimulus. Build scalable automation in Python, integrate VIP, define coverage metrics, debug RTL/testbench/software interactions, and drive verification best practices across teams.

Top Skills: C++Constrained-Random GenerationDdr5EthernetFormal VerificationFunctional CoverageGenerative Ai/LlmsHbmNoc (Network-On-Chip)Pcie Gen5Pcie Gen6PythonRtlSva (Systemverilog Assertions)SystemverilogTestbench DevelopmentUpf (Power-Aware Verification)UvmVerification Ip (Vip)

Micron Technology

Principal Engineer

5 Days Ago

In-Office

168K-336K Annually

Senior level

168K-336K Annually

Senior level

Artificial Intelligence • Hardware • Information Technology • Machine Learning

The Staff/Principal Engineer will lead DDR interface verification for SoCs, working cross-functionally to define test requirements, create verification plans, and support simulation and emulation platforms.

Top Skills: CC++Ddr5Ddr6Lpddr6Soc

SpaceX

Sr. ASIC Design Verification Engineer (Silicon Engineering)

2 Days Ago

In-Office

165K-230K Annually

Senior level

165K-230K Annually

Senior level

Aerospace • Other

The engineer will handle digital ASIC verification, develop and execute test plans, and conduct pre- and post-silicon validation for cutting-edge ASICs at SpaceX.

Top Skills: AsicOvmPythonUvmVmm

What you need to know about the Boston Tech Scene

Boston is a powerhouse for technology innovation thanks to world-class research universities like MIT and Harvard and a robust pipeline of venture capital investment. Host to the first telephone call and one of the first general-purpose computers ever put into use, Boston is now a hub for biotechnology, robotics and artificial intelligence — though it’s also home to several B2B software giants. So it’s no surprise that the city consistently ranks among the greatest startup ecosystems in the world.

Key Facts About Boston Tech

Number of Tech Workers: 269,000; 9.4% of overall workforce (2024 CompTIA survey)
Major Tech Employers: Thermo Fisher Scientific, Toast, Klaviyo, HubSpot, DraftKings
Key Industries: Artificial intelligence, biotechnology, robotics, software, aerospace
Funding Landscape: $15.7 billion in venture capital funding in 2024 (Pitchbook)
Notable Investors: Summit Partners, Volition Capital, Bain Capital Ventures, MassVentures, Highland Capital Partners
Research Centers and Universities: MIT, Harvard University, Boston College, Tufts University, Boston University, Northeastern University, Smithsonian Astrophysical Observatory, National Bureau of Economic Research, Broad Institute, Lowell Center for Space Science & Technology, National Emerging Infectious Diseases Laboratories