Top Tech Jobs & Startup Jobs in Boston, MA

Provide expert-level technical support for NVIDIA DGX compute/GPU platforms: triage and resolve hardware and software issues on multi-distro Linux, debug installations and interoperability, coordinate with engineering/marketing, create KB articles, and improve support processes. Interact directly with customers via phone/email/conference and apply AI tools for debugging and documentation.

Analyze and optimize HPC application performance across CPU and multi-node multi-GPU systems by driving compiler and library improvements. Port and tune applications, evaluate compiler/runtime/driver impacts, and collaborate with compiler development and application engineering teams to deliver performance enhancements.

As a Senior Solutions Architect, you will assist customers in building solutions with NVIDIA's AI technology, focusing on Generative AI and Large Language Models while collaborating across teams for performance analysis.

The role involves developing and optimizing the Flang Fortran compiler, improving features in LLVM, and addressing HPC compilation challenges.

Design and maintain system software for GPU communication, develop architectural solutions for computing platforms, and work with cross-disciplinary teams.

As a Senior DFT Engineer, you'll develop DFT architecture for AI Chips, collaborating on DFT methodologies and ensuring product quality.

Develop AI systems for efficient inference, design and optimize kernels, and build domain-specific compilers and runtimes while collaborating with engineers.

The Senior Formal Verification Engineer will verify sophisticated ASIC builds using formal methods, collaborate with architecture teams, develop verification environments, and support silicon debug.

As a Senior GPU Architect, you'll design and implement GPU profiling features, contribute to hardware models, and work with interdisciplinary teams to improve performance insights.

Lead full-flow physical implementation for LPU ASICs: synthesis, floorplanning, place & route, timing closure, UPF/LEC low-power flows, and tapeout. Collaborate with IP, front-end, PnR and sign-off teams to optimize PPA and resolve bottlenecks. Architect automated, data-driven EDA methodologies, implement scripts and AI-assisted optimizations, and ensure sign-off quality including power grid, EMIR, and DFT integration for high-speed SerDes blocks.