Design and deliver secure compute hardware for post-quantum cryptography and orbital/terrestrial systems. Own power, thermal, enclosure, and bus architecture design; collaborate with software, security, and systems teams; support FPGA integration, manufacturability, reliability, and environment-specific constraints (radiation, vibration, thermal-vacuum). Deliver iterative hardware releases on aggressive timelines.

Lead engineering of core scheduling and orchestration subsystems for an orbital edge compute platform. Own an MVP for autonomous scheduling across compute node fleets, scale to larger satellite fleets with data sovereignty, design performant and reliable distributed engines, build scheduling and workload-placement logic for intermittent-connectivity edge environments, and provide technical leadership while partnering with cross-functional teams to deliver secure, customer-focused solutions.