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The engineer will define and implement ASIC package architecture, focusing on FC-BGA and MCM solutions, collaborating on package design and ensuring successful production of high-performance ASICs.

The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.

As an ASIC Synthesis and Timing Engineer, you'll implement complex SoCs for satellite systems, develop timing constraints, optimize PPA, and ensure design integration with partners.

The Senior ASIC Physical Design Engineer will oversee the full physical design flow for complex SoCs, ensuring timing closure and optimization while collaborating with various teams and external providers on satellite projects.

Lead the implementation of complex SoCs for satellite systems, managing the RTL-to-GDSII flow, collaborating with design teams, and ensuring silicon success in advanced technologies.

The Principal ASIC Design Verification Engineer is responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams on design-for-verification practices and silicon validation.

The Senior ASIC Design Verification Engineer will verify custom silicon designs, develop verification plans, drive test strategies, and collaborate with various engineering teams.

The ASIC Design Verification Engineer will verify silicon designs, develop verification plans, execute tests, and manage simulation environments, ensuring high quality and functionality through rigorous testing and collaboration with cross-functional teams.

The RFIC Layout Designer will lead the implementation of RF and mixed-signal ICs, focusing on layout strategies, top-level integration, and collaborating with various teams to ensure successful silicon tapeouts.

The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.