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Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel/FIRRTL). Improve multi-core coherence, integrate designs into toolchain, perform sandbox verification, collaborate with verification teams, and produce documentation and tests.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

Design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as configurable RTL generators (Chisel/Scala). Integrate designs into the Chisel/FIRRTL framework, enable automatic config/verification flows, perform sandbox verification, collaborate with verification teams, and produce documentation.

Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.