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Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Define end-to-end formal verification strategies for complex SoCs and IP subsystems. Identify high-risk architectural issues, develop formal methodologies, manage abstractions, drive proof convergence, and improve implementations for correct-by-construction designs. Lead verification across large hardware systems, including CPU microarchitecture, communication fabrics, and protocols, using formal methods and simulation co-verification.

Lead verification for a cache-coherent interconnect subsystem based on ARM CHI. Develop verification environments, protocol checkers, scoreboards, assertions, coverage models, and constrained-random tests covering coherency, ordering, flow control, retries, and integration. Analyze failures across specifications, RTL, and testbenches; drive verification strategy, coverage closure, methodology improvements, and durable fixes. Collaborate with architecture, design, formal, and software teams while mentoring engineers and supporting signoff.

Develop and maintain SiFive’s verification platform infrastructure, libraries, tools, and methodologies for design verification. Build functionality using Chisel and CIRCT, create Scala-based verification libraries and generators, and develop Python tools for querying design intent and metadata. Collaborate with platform technology teams, support end-to-end verification flows, and educate teams on best practices. The role requires compiled and scripting language experience, modern software engineering knowledge, and experience deploying production software.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.