Top Remote Senior Level Hardware Engineer Jobs in Boston, MA

The Engineering Manager will lead a team to develop innovative Coffee & Beverage products, ensuring KPI critical subsystem designs and smooth execution from concept to production while representing engineering in high-level discussions.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

As a Senior Hardware Engineer, you'll drive DPU integration into server platforms, execute validation testing, and develop automation for data analysis while collaborating with cross-functional teams and vendors.

Lead design and implementation of digital IC/ASIC/SoC for medical imaging technology, owning RTL and validation processes with collaboration across teams.

The SOC Architect will lead the development of high-performance SoCs, defining security features, and collaborating with product teams and customers to deliver system IPs.

Owner of micro-architecture and RTL lifecycle for complex digital blocks. Implement RTL in SystemVerilog/Verilog, drive control logic and IP integration, support sign-off (CDC, RDC, lint, synthesis), collaborate with DV teams for closure and debug, and take full project ownership with minimal supervision.

The PIC Architect is responsible for designing advanced silicon photonics integrated circuits, managing PIC development, and coordinating with cross-functional teams to optimize performance and manufacturing processes.

Lead invention of AI-driven ASIC development methodology, identify cross-stage bottlenecks, build scalable data pipelines, define metrics, mentor engineers, and evaluate AI/EDA research to improve predictability and cycle time.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.