Staff Mixed Signal Design Engine, HBM

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• Define micro‑architecture for base‑die digital subsystems, including high‑bandwidth memory (HBM) channel support logic, initialization and boot sequencing, training orchestration, configuration and control registers (CSR), telemetry, performance counters, and reliability features such as error logging and recovery sequencing.
• Translate system requirements into timing, power, and area budgets with physical layer (PHY) and system architects, and maintain interface specifications for bus protocols, clock‑domain crossing (CDC) strategy, and reset strategy.
• Implement synthesizable register‑transfer level (RTL) designs in SystemVerilog and integrate multi‑channel logic, including interrupts, events, register maps, scan hooks, and design‑for‑test (DFT) interfaces.
• Ensure stable reset and power‑up behavior, support corner‑case handling, and maintain clear engineering change order (ECO) pathways.
• Collaborate with design verification (DV) teams to create verification plans, achieve coverage goals, complete CDC and reset‑domain crossing (RDC) checks, and debug RTL, testbench, and gate‑level issues.
• Provide guidance on timing constraints for clocks, exceptions, and path intent, and refine micro‑architecture to address timing‑critical paths.
• Partner with DFT and test teams to integrate scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), boundary access, and debug instrumentation.
• Support post‑silicon validation by supplying debug hooks, correlating issues to RTL or architecture, and enabling efficient issue resolution.

• Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering or Computer Engineering.
• Typically 10+ years in digital design or system‑on‑chip (SoC) integration with ownership of complex logic through tape‑out.
• Expertise in SystemVerilog RTL design, integration, and debug; clock and reset architecture; CDC and RDC methodologies; and low‑power design concepts such as clock gating and power‑state management.
• Knowledge of design‑for‑debug and design‑for‑test fundamentals and experience coordinating multi‑functional technical efforts.

• Experience supporting post‑silicon validation through debug correlation and structured issue resolution.
• Background integrating scan, MBIST, LBIST, and related DFT or debug features.
• Experience developing verification plans and partnering with DV teams to reach coverage goals.
• Ability to refine micro‑architecture to improve timing and provide mentorship on constraints.

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