Senior Principal Hardware System Architect

Role Overview

The AI infrastructure landscape is evolving at breakneck speed, and Astera Labs is at the center of it — delivering the intelligent connectivity solutions that enable the most demanding AI and cloud workloads on the planet. As server platforms grow increasingly complex with multi-socket architectures, accelerator-dense configurations, and high-speed interconnect fabrics, the need for world-class hardware architects who can define and deliver these systems end-to-end has never been more critical.

The AI Platform Solutions Group is seeking a Senior Principal Hardware / System Architect to lead the architecture, design, and development of next-generation x86 and accelerator-based server platforms. You will own system-level architecture decisions spanning compute, memory, storage, and interconnect subsystems — driving hardware platform development from concept through bring-up and validation. This role sits at the intersection of silicon, board design, FPGA/ASIC development, and platform integration, with direct impact on how AI infrastructure scales at the rack and cluster level.

This is a high-impact technical leadership role where you will partner across hardware, firmware, and platform engineering teams while collaborating with customers, silicon vendors, and hyperscalers to deliver custom, high-performance compute solutions. If you thrive on solving the hardest hardware architecture challenges and want to shape the platforms that power the next wave of AI, this is the opportunity.

Key Responsibilities

• System Architecture & Platform Design
  • Lead end-to-end system architecture and design for server platforms including x86 multi-socket and accelerator-based systems
  • Define and maintain multi-platform design standards and architectures that scale across product lines
  • Drive hardware platform development including board design, system bring-up, and validation
  • Oversee system-level integration across compute, storage, and interconnect subsystems — including PCIe Gen5/6 and high-speed fabric connectivity
• FPGA & Hardware Development Leadership
  • Lead FPGA architecture and development including simulation, synthesis, validation, and common framework definition
  • Drive signal integrity analysis, functional validation, and defect resolution across complex hardware systems
  • Own hardware debug and bring-up in lab environments, ensuring seamless integration with firmware and software stacks
• Cross-Functional & Customer Engagement
  • Provide technical leadership and mentorship to distributed engineering teams across hardware, firmware, and platform disciplines
  • Coordinate cross-functional activities to ensure alignment between hardware design, firmware integration, and system validation
  • Collaborate with customers and stakeholders on custom system solutions, technical briefings, and field issue resolution
  • Partner with silicon vendors, OEMs, and hyperscalers to drive platform innovation aligned with Astera Labs' connectivity ecosystem

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 12+ years of experience in hardware development or system architecture
• Deep expertise in x86 server architecture, including multi-processor systems
• Experience with FPGA and/or ASIC design including simulation, synthesis, and validation
• Strong knowledge of high-speed interconnects (PCIe, UPI/QPI, Ethernet) and signal integrity principles
• Proven experience with system bring-up, debug, and validation in lab environments
• Experience leading complex hardware programs and cross-functional engineering teams
• Strong knowledge of memory subsystems, cache coherency, and PCB design

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
• Experience with accelerator-based systems (GPU, AI/ML workloads) or AI training cluster hardware
• Familiarity with heterogeneous computing architectures or composable infrastructure
• Experience with EDA tools such as Cadence, Allegro, Quartus, or Xilinx environments
• Programming experience in C, Python, or scripting languages for hardware automation and validation
• Background in enterprise server, data center hardware, or custom system development
• Experience working with global development teams and customer-facing engineering engagements
• Knowledge of fault-tolerant design or secure communication systems