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Raydar

Principal Analog/Mixed Signal Engineer

Posted 6 Days Ago
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In-Office
Boston, MA, USA
200K-325K Annually
Senior level
In-Office
Boston, MA, USA
200K-325K Annually
Senior level
Lead analog and mixed-signal circuit design for semiconductor chips, owning major architecture areas from concept through fabrication. Design circuits, create physical layouts, perform DRC, ERC, and LVS checks, and collaborate across engineering disciplines. Characterize returned silicon using bench test equipment. The role requires CMOS expertise, Cadence simulation proficiency, multiple fabricated chips, and a master’s or PhD in Electrical Engineering.
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About the company

Our client is a semiconductor company.

The role

Raydar is recruiting for this role on behalf of our client. Take technical leadership of custom circuit design for upcoming silicon releases, owning significant parts of the chip architecture. The position blends hands-on design, layout and checking with bench evaluation of returned silicon, working alongside colleagues from several technical disciplines.

What you'll do

- Direct the development of circuits that mix analog and digital behavior, including data converters, timing and clock generation, power regulation, reference sources and fast serial interfaces.

- Take ownership of substantial portions of the chip architecture, with the possibility of serving as lead on one of several planned devices.

- Draw physical layouts yourself and run the standard design rule, electrical rule and layout-versus-schematic checks.

- Partner with teammates in circuit design, systems, physics and software to turn novel concepts into working silicon.

- Help characterize returned silicon on the bench with common test and measurement instruments.


Requirements

What we're looking for

- Track record of creating circuits that combine analog and digital functions, such as clock synthesizers, serial links, converters and oscillators, rather than analog-only work.

- Strong command of analog and mixed-signal design in CMOS technology.

- Several chips taken through fabrication, ideally in FinFET or 28nm/65nm processes.

- Master's or PhD in Electrical Engineering with a circuits or integrated circuit design emphasis.

- Fluency with Cadence simulation flows, including parasitic extraction, Monte Carlo and process corner analysis.

- Around 6 or more years of relevant experience.

- Readiness to pitch in wherever the team needs help, even beyond your main area, in a startup environment.

- Based in the Boston area or willing to relocate there.

Bonus points

- Practical experience drawing layouts yourself, beyond reviewing them.


Benefits

Compensation and benefits

- Base salary: USD 200,000 to 325,000 per year

- Equity

Location and work model

- Boston, MA, United States

- Hybrid: 3 days per week in office

- Full-time

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