Networking ASIC Architect

Tenstorrent is seeking a Networking ASIC Architect to help define next-generation high-performance networking architectures for AI/ML and datacenter systems. This is a highly technical role requiring deep domain expertise in ASIC design, data movement protocols, and programmable networking paradigms. You will work cross-functionally with design teams to drive architecture, microarchitecture, and performance modeling of complex networking systems.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems thinker who understands how network architecture affects end-to-end system performance.
• Passionate about designing scalable, low-latency solutions that support massive AI and HPC workloads.
• Comfortable diving into both hardware RTL and system-level performance modeling.
• A strong communicator who can collaborate across architecture, design, software, and silicon teams.
• Driven by curiosity, with a bias for action and the persistence to drive architectural innovation.

What We Need

• 5+ years of experience in networking chip design with hands-on RTL design expertise.
• Deep knowledge of buffering and queuing mechanisms, especially in networks with ≥25 Gbps per port.
• Strong grasp of packet forwarding, scheduling algorithms, and transport protocols (L2/L3/L4: e.g., RDMA, RoCE, TCP/UDP, nARQ).
• Experience in traffic modeling and performance-driven ASIC architecture.
• Knowledge of how IP components combine to form a networking interface (SERDES→ PCS→ MAC→ etc.) and how they impact accelerators/IP that sit above them.
• Understanding of multi-hop switching, traffic congestion control, and head-of-line blocking mitigation.

What You Will Learn

• How to co-architect silicon for AI, networking, and data movement in chiplet-based SoC designs.
• Exposure to next-gen connectivity technologies tailored to ML inference, training clusters and heterogeneous systems.
• Collaborate with architects, designers, and system modelers to deliver industry-shaping networking silicon.
• Deepen understanding of system-wide bandwidth optimization and programmable packet processing pipelines.
• Contribute to the evolution of networking for hyperscale AI workloads and distributed systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.