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Cadence Design Systems

Digital Flow Enablement Solutions Architect

Reposted 3 Days Ago
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In-Office
Burlington, MA, USA
158K-293K Annually
Expert/Leader
In-Office
Burlington, MA, USA
158K-293K Annually
Expert/Leader
The role involves leading customer engagements in digital flow enablement, conducting design experiments, validating timing flows, and collaborating with R&D on tool improvements.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Locations: remote role but must be currently located in the US.

The position involves:

  • Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development.
  • Interfacing with customers regarding digital flow enablement and methodologies, including:
    • timing characterization, including sensitivity modeling,
    • Physical view generation (LEF, GDS, abstracts, etc)
    • Logical view generation (LIB, CDL, Spectre, etc)
    • Technology LEF creation for digital tools
    • MSOA flows
  • Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness
  • Tempus timing flow development and validation
  • Working closely with R&D on tools and methodology improvements
  • Other digital P&R tasks as needed by the group
  • Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes

Position Requirements:

  • Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
  • Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects
  • Excellent digital simulation and debug skills
  • Experience with techLEF development at advanced nodes a must
  • Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM
  • Strong knowledge of Digital Design flows and Static Timing Analysis
  • Prior experience with ASIC digital implementation flows and EDA tools is required
  • Experience with advanced nodes (5nm and below) required.
  • Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
  • Strong customer-facing communication and problem solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Excellent verbal and written communication skills

Familiar with EDA tool:

  • Characterization: Liberate, Liberate MX, Liberate AMS
  • Simulators: Spectre, AMS, Xcelium
  • Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc

The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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