Design for Test (DFT) Engineer, Principal

About Positron AI

Positron AI specializes in developing custom hardware systems to accelerate AI inference.  These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt.  Positron exists to create the world's best AI inference systems.

Role Overview

Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.

Key Responsibilities

Own the Positron DFT strategy

• Define and maintain the DFT architecture for Asimov and future ASIC generations.
• Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives.
• Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization.

Hands-on DFT implementation

• Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features.
• Integrate DFT into internally developed RTL.
• Evaluate and integrate DFT capabilities from third-party IP providers.
• Work directly in RTL, synthesis, and DFT tool flows.

Drive pre-silicon DFT verification

• Develop comprehensive DFT verification plans.
• Validate DFT functionality through simulation and gate-level verification.
• Ensure structural coverage targets are achieved before tapeout.
• Drive DDA, stuck-at, transition, cell-aware, and power-aware ATPG strategies.
• Own DFT signoff.

Partner with Physical Design

• Work closely with backend implementation teams to ensure successful physical realization of DFT architecture.
• Guide scan chain partitioning, compression planning, and test clock architecture.
• Address power-aware test implementation, timing closure considerations, and test mode integration.

Own external DFT execution

• Serve as Positron's technical lead for all DFT work performed by external design services partners.
• Review implementation quality and conduct design reviews.
• Drive issue resolution.
• Define deliverables and acceptance criteria.
• Ensure external work meets Positron quality standards.

Cross-functional leadership

• Partner closely with RTL designers, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT is designed in from architecture through silicon bring-up.

AI-enabled engineering

• Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG analysis, coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
• Continuously evaluate new AI techniques that accelerate DFT development while improving quality.

Required Qualifications

• BS, MS, or PhD in Electrical Engineering or Computer Engineering
• 12+ years of ASIC development experience
• Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts
• Strong understanding of scan architectures, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, test compression, fault models, and structural coverage analysis
• Experience with leading DFT tool suites (e.g., Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or equivalent)
• Strong RTL skills using Verilog/SystemVerilog
• Experience with synthesis and gate-level verification
• Strong scripting skills (Python, Tcl, Perl, or similar)
• Excellent debugging skills across RTL, netlists, and silicon test
• Demonstrated ability to drive technical execution across cross-functional engineering teams

Preferred Qualifications

• Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures
• High-speed SerDes and advanced process nodes (5nm and below)
• Low-power design, yield enhancement methodologies, and manufacturing test optimization
• Silicon bring-up, failure analysis, and post-silicon debug
• Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test
• In-system debug and observability: experience architecting debug infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up
• Emulation and pre-silicon validation: familiarity with Palladium/ZeBu/Veloce or FPGA prototyping to validate DFT features before tapeout
• Third-party IP integration: experience auditing, integrating, and validating DFT collateral from multiple IP vendors to ensure a coherent full-chip DFT architecture, not just block-level stitching

Leveling & Scope

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

Why Join Us?

• Be part of a rapidly growing AI startup shaping the future of AI hardware
• Work on groundbreaking technology with a highly skilled and passionate team
• Competitive salary, equity, and comprehensive benefits package
• Flexible work environment with remote work options

If you are excited about ensuring the highest quality AI hardware and leading an advanced team, we want to hear from you! Apply today.

Compensation and Benefits

The base salary range for this role is $200,000 – $350,000.

Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.

We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.

Health and wellness

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available

Time off and flexibility

• Unlimited paid time off — we encourage everyone to truly unplug and recharge
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup

Compensation and future

• Competitive salary and equity
• 401(k) with company matching, eligible from day one

This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.

Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.