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NVIDIA

ASIC Design Verification Engineer - New College Grad 2026

Reposted 5 Hours Ago
In-Office
Austin, TX
108K-213K Annually
Entry level
In-Office
Austin, TX
108K-213K Annually
Entry level
As an ASIC Design Verification Engineer, you'll verify system-level designs, create verification environments, perform regression tests, and collaborate with other engineers to improve methodologies.
The summary above was generated by AI

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at NVIDIA working on a system-level IP responsible for measuring performance on multiple projects. Your focus will be on verifying and improving the related verification methodologies for the corresponding design (RTL). For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC).

What you'll be doing:

  • Design and maintain the unit level/sub-system Verification environment.

  • Understand the architecture specifications, develop and carry out the test plan to verify the design.

  • Create the UVM components, sequences, tests and scoreboards.

  • Sign off on the verification efforts with very high quality code and functional coverage.

  • Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets

  • Automate the manual steps involved in launching build, regression, and triages.

  • Collaborate with architects, designers, and software engineers to achieve the project goals.

  • Pro-actively contribute to improving the efficiency of the testbenches by embracing the latest techniques.

What we need to see:

  • Completing an MS or higher in Computer or Electrical Engineering (or equivalent experience).

  • Experience in System Verilog, UVM and in general OOPS based programming.

  • Strong coding skills in Python or other industry-standard scripting languages.

  • Strong understanding of RTL design (Verilog).

  • Good understanding of computer architecture fundamentals.

  • Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.

With industry-leading salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. The most forward-thinking engineers in the world do their life’s work at NVIDIA. If you're creative and autonomous, with a real passion for technology, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until January 13, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Python
System Verilog
Uvm
Vcs
Verdi
Verilog

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