Teams at Tylsemi

The CAD/Flow Methodology Development leader will define and scale EDA infrastructure, automate design flows, debug issues, and establish metrics for silicon delivery efficiency in cross-functional environments.

The Design Verification Engineer ensures functional correctness of IPs and SoCs by developing verification environments, driving coverage closure, and automating tasks to enhance productivity.

The role involves end-to-end recruitment and talent management for semiconductor roles, designing onboarding and training strategies, and ensuring strong stakeholder communication.