Jobs at Tenstorrent Inc.

Lead go-to-market positioning and messaging for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, benchmarks, demos, sales decks), and field enablement. Partner closely with product, engineering, sales, and marketing to align roadmap, launches, and customer solutions. Translate technical capabilities into business value for enterprise, cloud, and regulated markets while gathering customer and competitive insights to inform strategy.

Lead R&D on LLM training and inference optimization, train and evaluate large-scale models on Tenstorrent hardware, improve performance via techniques like speculative decoding, quantization, kernel fusion, flash attention and distributed training, diagnose system bottlenecks, and translate research into scalable production solutions through cross-functional collaboration.

Senior-level program manager and chief of staff supporting the CVP of Operations. Own and drive high-priority cross-functional programs from kickoff through execution, establish operating cadences, align teams on priorities, prepare leadership materials, integrate sales & operations, headcount and infrastructure planning, surface risks, and remove execution blockers to ensure organizational KPIs and milestones are met.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

Own and drive end-to-end product certification and regulatory compliance to enable customer shipments and revenue. Coordinate Sales, Systems Engineering, Operations, Manufacturing, and external agencies; remove roadblocks, manage escalations, track timelines and risks, and ensure products meet global import/export and regional regulatory requirements.

Lead go-to-market positioning and solution strategy for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, decks, benchmarks, demos), and customer stories. Partner with product, engineering, sales, and marketing to align roadmaps, launches, and field enablement, translating deep technical capability into clear customer outcomes.

Run deal governance, escalation management, and cross-functional coordination to remove blockers and accelerate sales execution. Partner with Sales, Legal, Finance, Trade Compliance, and Operations to manage deal logistics, contract review, forecast support, S&OP, incentive reconciliation, and CRM-driven processes to scale GTM operations.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

Lead and scale accounting operations (AP, AR, payroll accounting, fixed assets, accruals, reconciliations, and close). Improve close cycle, strengthen internal controls, drive ERP/process automation, build a high-performing global team, and manage auditors, consultants, and outsourced partners to support rapid growth and public-company readiness.

Own Tenstorrent's developer platform including firmware, system software, packaging, updates, and a unified CLI. Define roadmap, prioritize engineering work, partner with DevRel and customers, ship iterative improvements, and measure success via developer NPS and CLI adoption.

Design and implement full‑custom analog/mixed‑signal layouts for high‑performance IP in advanced FinFET nodes. Translate schematics to manufacturable layouts, optimize floorplans for PPA and matching, run and close physical verification (DRC/LVS/ERC/DFM/antenna), perform post‑layout extraction/simulation, and integrate blocks into SoCs. Develop layout automation and collaborate with circuit designers to meet performance, noise, and reliability targets.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

Define and own chiplet-based compute platform architectures for high-performance RISC-V CPUs in SiP solutions. Lead design of PCIe, die-to-die connectivity, coherent fabrics, system management, and confidential computing subsystems. Collaborate with architecture, hardware, software, and external IP partners to deliver production-ready chiplet architectures and drive cross-functional execution.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.