Jobs at SiFive

Develop and maintain SiFive’s verification platform infrastructure, libraries, tools, and methodologies for design verification. Build functionality using Chisel and CIRCT, create Scala-based verification libraries and generators, and develop Python tools for querying design intent and metadata. Collaborate with platform technology teams, support end-to-end verification flows, and educate teams on best practices. The role requires compiled and scripting language experience, modern software engineering knowledge, and experience deploying production software.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as configurable RTL generators (Chisel/Scala). Integrate designs into the Chisel/FIRRTL framework, enable automatic config/verification flows, perform sandbox verification, collaborate with verification teams, and produce documentation.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel/FIRRTL). Improve multi-core coherence, integrate designs into toolchain, perform sandbox verification, collaborate with verification teams, and produce documentation and tests.

Design and implement configurable TileLink interconnects, cache controllers, protocol bridges and other uncore infrastructure as RTL generators in Chisel. Integrate with SiFive's Chisel/FIRRTL framework, perform initial sandbox verification, collaborate with verification teams on test plans, document designs, and improve generator tooling for automatic configuration, verification, and packaging.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.

The SOC Architect will lead the development of high-performance SoCs, defining security features, and collaborating with product teams and customers to deliver system IPs.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel). Integrate designs into SiFive's Chisel/FIRRTL framework, enable automatic configuration, verification, and documentation, and collaborate with verification teams and peers to deliver high-performance, configurable interconnect IP.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Lead verification strategy and execution for a cache-coherent interconnect subsystem, defining plans, assertions, checkers, scoreboards, and coverage. Develop directed and constrained-random scenarios, drive cross-team verification across interfaces and bridges, apply simulation/formal/emulation as appropriate, perform root-cause analysis, and mentor engineers to raise verification quality and reusable infrastructure for high-performance CPU/SoC platforms.

Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.

Design and microarchitect power-management, reset, and clocking solutions for high-performance CPU and SoC IP. Develop RTL, spec microarchitecture, run sandbox verification, collaborate with verification, physical implementation, and software teams to optimize frequency, area, and power and drive designs through tapeout.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.