Search the 13 jobs at Apple

Seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. Responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.

As a CPU Top-Level Verification Engineer, responsible for defining effective verification methodology, developing test plans, test benches, and test environments, driving coverage convergence, and maintaining efficient testbench environments for high-performance lower power processor designs at Apple.

In this role, you will work on silicon timing correlation for Apple chip design efforts, debugging physical issues in silicon, and correlating timing behavior with pre-silicon models.

Experienced CPU RTL Architect responsible for microarchitecture development, RTL design, verification, performance exploration, and design delivery for Apple's Silicon Engineering Group.

Seeking an experienced CPU RTL Architect with knowledge in microprocessor architecture, RTL design, verification, and performance exploration. Must have expertise in Verilog, VHDL, C, C++, and scripting languages like Perl and Python.

Develop and test embedded software for Apple's Wireless SoCs, debug silicon issues, and collaborate with designers and architects. Architect and scale test frameworks for large-scale testing, and support product development builds. Requires 3+ years of industry experience.

Responsible for physical implementation of design partition(s) for a highly complex SoC using state-of-the-art process technology. Familiar with timing of large high-performance SoC designs in sub-micron technologies, STA, noise, crosstalk, and ECO techniques. Strong programming skills in Perl and TCL.

Seeking an experienced CPU RTL Architect to lead CPU multi-level cache subsystem architecture and RTL development for multi-processor systems at Apple's Silicon Engineering Group. Responsibilities include micro-architecture development, RTL ownership, verification support, performance exploration, and design delivery.

Join Apple's Silicon Engineering Group as a Senior Analog Layout Engineer to contribute to the evolution of Analog/Mixed-Signal circuits and optimize the performance of Apple's products. Craft custom analog designs, collaborate with circuit designers, and work with multidisciplinary teams in a dynamic environment. Must have 10+ years of experience in analog layout design, familiarity with deep submicron CMOS circuits and FinFET technologies, programming knowledge in SKILL, Perl, TCL, Shell, Python, and expertise in analog layout designs.

As an Analog Mixed-Signals Methodology Engineer at Apple, you will be responsible for building and supporting innovative design methodology and customizing flows for mixed-signal IP designs. This role involves collaborating with mixed signal design teams, CAD teams, and EDA vendors to enhance design processes and drive improvements. Strong technical skills in SPICE simulation, programming languages, and flow automation are required. The position also entails prototype development, debugging, tool deployment, and providing training to design teams.

Design and customize flows for mixed-signal IP designs, collaborate with teams and vendors, and provide innovative solutions for high-performance design methodologies.

Seeking a results-oriented Analog Mixed Signal IP Designer at Apple to work on PHY design effort collaborating with architecture and logic design teams. Responsibilities include generating gate level netlist, lint, logic equivalence check, static low power verification, CDC, RDC, and leading collaterals between front-end and physical design teams.

As a Physical Design Engineer at Apple, you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of the final GDSII. Responsibilities include generating timing constraints, building floor plans, developing clock networks, place and route, ECO implementation, and guiding other designers in fixing design violations.